Input Output

 INPUT OUTPUT ARCHITECTURE (PART 1)

 INTRODUCTION 

INPUT DEVICES
OUTPUT DEVICES
INPUT OUTPUT DEVICES

  • KEYBOARD
  • MOUSE
  • SCANNER
  • CD-ROM
  • GAME CONTROLLER

  • MONITOR
  • PRINTERS
  • DISK DRIVE
  • FLOPPY DRIVES
  • CDRW-ROM
  • SPEAKERS

  • MODEM
  • NETWORK INTERFACE CARD
  • PORTABLE ZIP DRIVES




DATA TRANSFER COMMUNICATION

SYNCHRONOUS

Data is sent via a bit-stream, which sends a group of characters in a single stream.Synchronous modems must be match with each other. They accomplish this by sending special characters.

ASYNCHRONOUS

Data is coded into a series of pulses, including a start bit(sending by sending modem) and a stop bit.Stop bit designating that the transfer of that bit is complete.



FUNCTION OF INPUT/OUTPUT MODULES

  • CONTROL AND TIMING
  1. Coordination of traffic between internal resources and external devices.
example transaction :
  1. processor interrogates status of I/O module
  2. module return devices status.
  3. I/O module obtains a byte of data from the devices.
  • CPU COMMUNICATING
  1. Data will exchange between CPU and module.Status reporting to CPU since peripherals are slow.Address recognition for the devices connected to it.

Processor communication involves :

  1. Command decoding : send as signal on control bus with parameters on data bus.
  2. Data exchange with processor.
  3. Status reporting : Peripherals are slow compared to processor.
  4. Address decoding : Module recognizes unique address for each devices it controls.
  • DEVICE COMMUNICATION
  1. On the other side I/O module has to communicate with the device : command,status information,data.
  • DATA BUFFERING
  1. Buffering is often essential.
  2. Handles the speed mismatch between memory and the device : low speed devices need to have data from memory buffered.
  • ERROR DETECTION
  1. Mechanical and electrical malfunction : out of paper, paper jam, bad disk sector.
  2. Data communication errors : typically detected with parity bits.

NUR DIYANA BINTI DZOLKIFLI
B031410414

INPUT OUTPUT ARCHITECTURE (PART 2)


TYPICAL I/O CONTROL STEPS

  • COMMUNICATION GOES ACROSS THE BUS
  1. CPU checks I/O module devices status
  2. I/O module returns status
  3. If ready, CPU request data transfer
  4. I/O module gets data from device
  5. I/O module transfers data to CPU
  6. Variations for output, DMA, etc.
    INPUT/OUTPUT MODULE STRUCTURE



    I/O MODULE DECISIONS

    • Hide or reveal device properties to CPU 
    Example : 
    Disks : LBA(logical block addressing) physical address(CHS) is hidden from CPU.
    • Support multiple or single device 
    most disk controllers handle 2 devices.
    • Control device functions or leave for CPU
    Example :
    1. video adapters with the Direct Draw interface
    2. But tape drives expose direct control to CPU.
    • Operating decisions
    Unix treats everything it can as a file.

    TERMINOLOGY

    • Device or input/output controller : relatively simple, detailed control left to CPU.
    • Input/Output Processor or Input/Output Channel
    1. Presents high-level interface to CPU.
    2. Often control multiple devices.
    3. Has processing capability.

    INPUT OUTPUT TECHNIQUE

    • PROGRAMMED I/O
    1. The CPU issues a command then waits for the I/O operations to be complete.The CPU is faster than the I/O module then method is wasteful.
    • INTERRUPT DRIVEN I/O
    1. Processor issues command
    2. Device proceeds and leaves processor free.

    • DIRECT ACCESS MEMORY(DMA)
    1. Devices exchanges data directly with memory.
    • MEMORY MAPPED I/O 
    1. Memory and I/O are treated as memory only. It means no signal like IO/M.
    • ISOLATED I/O
    1. Address space of memory and I/O is isolated. It uses IO/M signal.

    TYPES OF INPUT/OUTPUT COMMANDS

    • CPU issues address : identifies module(& device if > 1 per module)
    • CPU issues command : 
      1. Control - telling module what to do : spin up disk
      2. Test - check status : power? error?
      3. Read/Write : module transfers data via buffer from/to device.
    NUR SYAZWANI BINTI MAHADZIR
    B031410014

     INPUT OUTPUT ARCHITECTURE (PART 3)


    INPUT/OUTPUT CONTROLLERS



    FOUR DESIGN TECHNIQUES

    1. MULTIPLE INTERRUPT LINES  : In this method we have multiple lines like in IC 8085.
    2. SOFTWARE POLLING : ISR polls to find out the device which has interrupted. The CPU reads a status register.The method is time consuming.
    3. DAISY CHIN : The method is hardware polling. The ack signal propagates through and is stopped by the devices who is interrupted.
    4. BUS ARBITRATION : In this method the device first gets control of the bus and then raises an interrupt request for data transfer.The CPU issues an ack the devices gives  vector for branching.

    PROGRAMMED INPUT/OUTPUT

    1. CPU has direct control I/O : sensing status, read/write commands, transferring data.
    2. CPU waits for I/O module to complete operation.
    3. Wastes CPU time.
    • Programmed I/O-detail
    1. CPU request I/O operation
    2. I/O module performs operation
    3. I/O module sets status bits.
    4. CPU checks status bits periodically.
    5. I/O module does not inform CPU directly.
    6. I/O module does not interrupt CPU.
    7. CPU may wait or come back later.

      The code in the OS for programmed I/O be more like :

      keyboard_wait:               ; for get_ch
            test Keyboard_Status, 80000000h
            jz keyboard_wait
            mov eax, Keyboard_Data
      and
         display_wait:                   ; for put_ch
            test Display_Status, 80000000h
            jz display_wait
            mov Display_Data, eax

      This scheme is known as BUSY WAITING, or SPIN WAITING. 
      The little loop is called a SPIN WAIT LOOP.



      Programmed I/O flow chart.


      Programmed input/output [POLLING]


      PROGRAMMED I/O PROBLEM 

      1. Much time is wasted spin waiting.

      ADDRESSING I/O DEVICES
      1. Under programmed I/O data transfer is very much like memory access(CPU viewpoint)
      2. Each device given unique identifier
      3. CPU command contain identifier(address)

      INPUT/OUTPUT MAPPING
      • Memory mapped I/O
      1. devices and memory share an address space.
      2. I/O looks just like memory read/write.
      3. No special commands for I/O
      • Isolated I/O
      1. Separate address spaces
      2. Need I/O or memory select lines
      3. Special commands for I/O : limited set of commands

      INPUT OUTPUT ARCHITECTURE (PART 4)


      INTERRUPTS
      1. CPU interrupt request line triggered by I/O devices
      2. Interrupt handler receives interrupt
      3. Maskable to ignore or delay some interrupts.
      4. Interrupt vector to dispatch interrupt to correct handler.
      5. Interrupt mechanism also used for exceptions.
      • Interrupt Driven I/O
      1. overcome CPU waiting
      2. Avoids repeated checking of device by CPU (polling)
      3. I/O module interrupts when ready.
      • Interrupt Driven I/O basic operation
      1. CPU issues read command
      2. I/O module gets data from peripheral while CPU does other work.
      3. I/O module interrupts CPU
      4. CPU requests data
      5. I/O module transfer data.
      Interrupt-driven I/O flowchart


      Simple interrupt processing


      MULTIPLE INTERRUPTS
      1. Each interrupt line has a priority
      2. Higher priority lines can interrupt lower priority lines
      3. If bus mastering only current master can interrupt

      VECTORED INTERRUPTS
      1. A device requesting an interrupt can identify itself by sending a special code to the processor over the bus.
      2. Interrupt vector
      3. Avoid bus collision
      INPUT/OUTPUT TRANSFER MODE
      • Serial
      1. In band signaling
      2. Bit oriented
      3. Bit/byte word translation
      • Parallel
      1. Byte word oriented
      2. Out of band signaling
      3. IDE, SCSI.
      SERIAL TRANSFER
      • Asynchronous Clocking
      1. Master clock the transfer
      2. Slave derive clock from master
      • Synchronous clocking
      1. Independent clocking
      2. Verification by synchronization pattern
      PARALLEL TRANSFER
      • Data transfer
      1. Read sector
      2. Write sector
      • Control
      1. Disk seek
      • Transfer Intergrity
      1. Transfer parity
      2. Data encoding
      CONTROLLING DEVICE REQUESTS
      • Some I/O device may not be allowed to issue interrupt request to the processor.
      • At device end, an interrupt-enable bit in a control register determine whether the device is allowed to generate an interrupt request.
      • At processor end, either an interrupt enable bit in the PS register or priority structure determines whether a given interrupt request will be accepted.
      EXCEPTION
      • Recovery from errors
      • Debugging : trace, breakpoint
      • Privilege exception
      USE OF INTERRUPTS IN OPERATING SYSTEM
      • The OS and the application program pass control back and forth using software interrupts
      • Supervisor mode/user mode.
      • Multitasking
      • Process - running, runnable, blocked
      • Program state.
        INPUT OUTPUT ARCHITECTURE (PART 5)

        BUS ARBITRATION

        • The device that is allowed to initiate data transfers on the bus at any given time is called the bus master.
        • Bus arbitration is the process by which the next device to become the bus master is selected and bus mastership is transferred to it.
        • Need to establish a priority system.
        • Two approaches : centralized and distributed.


        Centralized Arbitration

        BUSES

        • The primary function of a bus is to provide a communications path for the transfer of data.
        • A bus protocol is the set of rules that govern the behavior of various devices connected to the bus as to when to place information on the bus,assert control signals.
        • Three types o bus linen : data, address , control.
        • The bus control signal also carry timing information.
        • Bus master(initiatior)/slave(target)
        ISA BUS INTERRUPT SYSTEM

        • ISA bus chains two 8259As together
        • Link is via interrupt 2.
        • Gives 15 lines : -16 lines less one for link
        • IRQ 9 is used to re-route anything trying to use IRQ 2: backwards compatibility.
        • Incorporated in chip set - you will not see a chip labeled "82591A" on a motherboard.
        PIC
        • The chip is called a"programmable interrupt controller" because it can be set up by the OS to use different operating modes :
        1. Fully nested : IRQs are priotized(settable by OS)
        2. Rotating : round-robin of equal priority interrupts
        3. Masks can be inhibit or enable interrupts
        4. Interrupts can be vectored to a different INT from the IRQ.

        WEBSITE LINK FOR EACH CHAPTER


        CHAPTER 12 :  INPUT OUTPUT ARCHITECTURE 

        TRUC TRUONG POWERPOINT

        MUSTAFA MOHAMED

        NOR EZREEN FARA BINTI KHALID - B031410024
        NUR DIYANA BINTI DZOLKIFLI - B031410414
        NUR SYAZWANI BINTI MAHADZIR - B031410014
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